As link speeds and port densities increase exponentially for data center networks, it is difficult for a shared memory system to keep up with the aggregated system bandwidth. To cope with bandwidth demand, data center switches often adopt a multi-slice architecture in which each slice is responsible for buffering data from a subset of ports within a switch. Hence, the bandwidth requirement for each slice can be greatly reduced. The buffer memory is statically allocated among different slices. Although the scalability of such systems can be linear, it is limited by inter-slice communication and memory efficiency.
In a data center deployment, there is a high possibility of uneven buffer utilization. That is, not all of the slices will be equally occupied at the same time. Some slices might be running out of buffering space while other slices might have low buffer utilization. How to efficiently, but simply, use the buffer memory based on the slice-architecture is a challenging problem.